Imec Achieves Breakthrough in Memory Technology with Advanced SOT-MRAM Devices

In a significant advancement in memory technology, imec, a leading research hub in nanoelectronics and digital technologies, presented its newest development in spin-orbit transfer magnetic random-access memory (SOT-MRAM) devices at the 2023 International Electron Devices Meeting (IEEE IEDM 2023). These devices have shown the best published performance ever, achieving a switching energy below 100 femto-Joule per bit and an endurance greater than 10^15, thereby bringing non-volatile SOT-MRAM technology closer to being used in last-level cache memory applications in high-performance computing (HPC).

SOT-MRAM is emerging as a promising candidate to replace static random-access memory (SRAM) as a last-level cache memory. It offers high switching speed, similar to SRAM, but with the added advantage of potentially unlimited endurance. Moreover, being nonvolatile, SOT-MRAM bit cells have a lower standby power than SRAMs at high cell density. These cells can potentially be made much smaller than SRAM cells, which translates into a higher bit packing density.

In their groundbreaking research, imec has experimentally explored the scaling potential and limitations of single perpendicular SOT-MRAM devices processed on 300mm wafers. This study, being the first of its kind on SOT-MRAM device scalability, revealed that scaling the SOT track not only reduces the footprint of the SOT-MRAM cell but also significantly improves the cell’s performance and reliability.

The core of this innovation lies in the design of the SOT track, a layer made of metal such as tungsten (W) or platinum (Pt) that resides below the magnetic tunnel junction (MTJ) – the actual switching element of the SOT-MRAM device. The SOT track serves as an in-plane current injection layer, crucial for de-coupling read and write paths. Sebastien Couet, program director of magnetics at imec, elaborates on the design process: “In conventional SOT-MRAM designs, the area occupied by the SOT track is larger than the actual MTJ pillar footprint to provide sufficient margin for overlay process control. But this results in wasted energy, as part of the current flows outside the MTJ area. We scaled SOT-MRAM devices to their extreme, with SOT track and MTJ pillar having comparable dimensions (critical dimension ~50nm). For these devices, we observed a switching energy below 100 femto-Joule (fJ) per bit, i.e., a reduction of 63% compared to conventional designs.”

Couet further explains the impact of scaling the SOT track on the memory’s endurance: “With an endurance beyond 10^15 program/erase cycles, we have experimentally validated our assumption that SOT-MRAM cells can have unlimited endurance – an important requirement for cache memories.”

The implications of this research extend to the future of circuit design in advanced technological environments. Imec is poised to continue their research with a focus on material engineering to further reduce the switching energy per bit and optimizing bit cell configuration to shrink the cell area compared to SRAM. Couet adds, “Our data provide valuable input for circuit designers to perform design-technology co-optimization (DTCO) of SOT-MRAM technology at advanced nodes – trading of performance improvement and design margins.” Imec also plans to transfer these learnings to the development of voltage-gated (VG) SOT-MRAM multi-pillar devices, which are aimed at high-density embedded memory applications.

Imec’s advancement in SOT-MRAM technology marks a critical step in the evolution of memory technologies, especially in the realm of high-performance computing. With its record low switching energy and exceptional endurance, imec's SOT-MRAM devices could revolutionize the efficiency and capacity of future computing systems.